Design and implementation of an all-digital timing recovery system for asynchronous communication
This work addresses the design and implementation of a timing recovery unit for a communication system with parallel reception, 4-PAM modulation, raised cosine filtering and a nominal sampling frequency of 1,1 GHz. The design of the building blocks within the system, as well as simulation results an...
| Autores Principales: | Valenciano-Rojas, José Jaime, Rímolo-Donadio, Renato |
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| Formato: | Artículo |
| Idioma: | Español |
| Publicado: |
Editorial Tecnológica de Costa Rica
2015
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| Acceso en línea: |
https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/2332 https://hdl.handle.net/2238/8735 |
| Sumario: |
This work addresses the design and implementation of a timing recovery unit for a communication system with parallel reception, 4-PAM modulation, raised cosine filtering and a nominal sampling frequency of 1,1 GHz. The design of the building blocks within the system, as well as simulation results and the physical implementation in FPGA are discussed. |
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