Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

https://www.scopus.com/inward/record.url?eid=2-s2.0-84945151182&partnerID=40&md5=6ddf5c2778c6b512bf6531ff81a9fd36

Autores Principales: Cerdas-Robles, Roberto, Rodríguez, Agustín, Julián, Pedro, Chacón-Rodríguez, Alfonso
Formato: Objeto de conferencia
Idioma: Inglés
Publicado: Institute of Electrical and Electronics Engineers Inc. 2017
Materias:
Acceso en línea: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7250489
https://hdl.handle.net/2238/7208
id RepoTEC7208
recordtype dspace
spelling RepoTEC72082022-04-09T03:05:25Z Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor Cerdas-Robles, Roberto Rodríguez, Agustín Julián, Pedro Chacón-Rodríguez, Alfonso Circuit, CMOS, aritmética, FPGA Circuitos CMOS Aritmética FPGA Research Subject Categories::TECHNOLOGY::Information technology::Computer science::Computer science https://www.scopus.com/inward/record.url?eid=2-s2.0-84945151182&partnerID=40&md5=6ddf5c2778c6b512bf6531ff81a9fd36 A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130nm low-power CMOS process, with an operation frequency of 100MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required. 2017-06-06T21:02:26Z 2017-06-06T21:02:26Z 2015-09 info:eu-repo/semantics/conferenceObject https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7250489 978-147998332-2 https://hdl.handle.net/2238/7208 eng Attribution-NonCommercial 3.0 Costa Rica https://creativecommons.org/licenses/by-nc/3.0/cr/ application/pdf Institute of Electrical and Electronics Engineers Inc. Circuits & Systems (LASCAS), 2015 IEEE 6th Latin American Symposium on Conference: 24-27 Feb. 2015
institution Tecnológico de Costa Rica
collection Repositorio TEC
language Inglés
topic Circuit, CMOS, aritmética, FPGA
Circuitos
CMOS
Aritmética
FPGA
Research Subject Categories::TECHNOLOGY::Information technology::Computer science::Computer science
spellingShingle Circuit, CMOS, aritmética, FPGA
Circuitos
CMOS
Aritmética
FPGA
Research Subject Categories::TECHNOLOGY::Information technology::Computer science::Computer science
Cerdas-Robles, Roberto
Rodríguez, Agustín
Julián, Pedro
Chacón-Rodríguez, Alfonso
Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
description https://www.scopus.com/inward/record.url?eid=2-s2.0-84945151182&partnerID=40&md5=6ddf5c2778c6b512bf6531ff81a9fd36
format Objeto de conferencia
author Cerdas-Robles, Roberto
Rodríguez, Agustín
Julián, Pedro
Chacón-Rodríguez, Alfonso
author_sort Cerdas-Robles, Roberto
title Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
title_short Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
title_full Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
title_fullStr Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
title_full_unstemmed Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor
title_sort design of an idm-based determinant computing unit for a 130nm low power cmos asic acoustic localization processor
publisher Institute of Electrical and Electronics Engineers Inc.
publishDate 2017
url https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7250489
https://hdl.handle.net/2238/7208
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score 12.238869