A methodology for the synthesis to logical netlist of an ASIC
Proyecto de Graduación (Maestría en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2017.
| Autor Principal: | Gurdián-Murillo, Mauricio |
|---|---|
| Otros Autores: | Castro-Godínez, Jorge |
| Formato: | Tesis |
| Idioma: | Inglés |
| Publicado: |
Instituto Tecnológico de Costa Rica
2017
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| Materias: | |
| Acceso en línea: |
https://hdl.handle.net/2238/7144 |
| id |
RepoTEC7144 |
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| recordtype |
dspace |
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RepoTEC71442023-04-25T17:36:41Z A methodology for the synthesis to logical netlist of an ASIC Gurdián-Murillo, Mauricio Castro-Godínez, Jorge Código ASIC Simulaciones Proyecto de Graduación (Maestría en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2017. The advances in technology for manufacturing ASICs allow more features to be added. As result, and depending on the architecture of the ASIC, more functional blocks do exist to support such additional features. This imply requiring more resources to synthesize each functional block into a logical netlist. As the physical design process is completed by a third party, reducing the time to deliver the complete set of synthesis files is critical for the project, so that the engineers can start the quality checks of each netlist earlier than the schedule, and the final product can be both completed and released on schedule. This work describes a methodology that automatically executes the synthesis flow of RTL code to logical netlist on each block that forms an ASIC. It helps keeping a better traceability of changes through the milestones in a project. A simulator of the methodology was implemented in Perl to validate that the complete synthesis runtime of an ASIC is improved, compared against a serial flow approach. Consequently, the time to synthesize the complete set of functional blocks is speedup 8.8 times. 2017-06-01T22:47:49Z 2017-06-01T22:47:49Z 2017 info:eu-repo/semantics/masterThesis https://hdl.handle.net/2238/7144 eng_US Attribution-NonCommercial-ShareAlike 4.0 International https://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Instituto Tecnológico de Costa Rica |
| institution |
Tecnológico de Costa Rica |
| collection |
Repositorio TEC |
| language |
Inglés |
| topic |
Código ASIC Simulaciones |
| spellingShingle |
Código ASIC Simulaciones Gurdián-Murillo, Mauricio A methodology for the synthesis to logical netlist of an ASIC |
| description |
Proyecto de Graduación (Maestría en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2017. |
| author2 |
Castro-Godínez, Jorge |
| format |
Tesis |
| author |
Gurdián-Murillo, Mauricio |
| author_sort |
Gurdián-Murillo, Mauricio |
| title |
A methodology for the synthesis to logical netlist of an ASIC |
| title_short |
A methodology for the synthesis to logical netlist of an ASIC |
| title_full |
A methodology for the synthesis to logical netlist of an ASIC |
| title_fullStr |
A methodology for the synthesis to logical netlist of an ASIC |
| title_full_unstemmed |
A methodology for the synthesis to logical netlist of an ASIC |
| title_sort |
methodology for the synthesis to logical netlist of an asic |
| publisher |
Instituto Tecnológico de Costa Rica |
| publishDate |
2017 |
| url |
https://hdl.handle.net/2238/7144 |
| _version_ |
1796142246186188800 |
| score |
12.041417 |